1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, relates to a semiconductor device which has the characteristic in electrode placement which makes easy heat dispersion of a power amplification element with high exothermic densities, such as GaN based Field Effect Transistors (FETs).
2. Description of the Related Art
A semiconductor device used with a high frequency band, for example, a microwave power amplifying device, is composed of active elements, such as FETs, passive elements, such as resistance and a capacitor, and circuit elements, such as microstrip lines for transmitting a high frequency signal. These circuit elements are formed, for example on a semi-insulating substrate. An electrode for grounding is formed on a backside of the semi-insulating substrate. And, when grounding the circuit element, the electrode for grounding formed on the backside of the semi-insulating substrate provided on the semi-insulating substrate is electrically connected with the circuit element through a VIA hole (via hole) which passes through the semi-insulating substrate, for example (for example, refer to Patent Document 1 and Patent Documents 2). Technology of others shown in Patent Documents 3 to 5 is disclosed.
As a shown in FIG. 1, for example, in a semiconductor device according to a conventional example, a gate electrode 24, a source electrode 20 and a drain electrode 22 have a plurality of fingers, and the plurality of fingers are governed every gate electrode 24, source electrode 20 and drain electrode 22 to form an electrode for terminals, on a substrate 10. As shown in FIG. 1, a part on which the gate electrode 24, the source electrode 20, and the drain electrode 22 have a plurality of finger shape forms an active area AA, and forms an exothermic part.
In an example of FIG. 1, gate terminal electrodes G1, G2, . . . , G4 and source terminal electrodes S1, S2, . . . , S5 are placed at the end of one side, and a drain terminal electrode D is placed at the end of another side.
Near the surface of the substrate 10, the active area AA is formed on the substrate 10 of the lower part of the gate electrode 24, the source electrode 20, and the drain electrode 22.
In the example of FIG. 1, in the source terminal electrodes S1 S2, . . . , S5, near the active area AA, VIA holes SC1, SC2, . . . , SC5 are formed from a backside of the substrate 10, and a ground conductor is formed on the backside of the substrate 10. And, when grounding the circuit element, the circuit element provided on the substrate 10 and the ground conductor formed on the backside of the substrate 10 are electrically connected through the VIA holes SC1, SC2, . . . , SC5 which pass through the substrate 10.
In addition, the gate terminal electrodes G1, G2, . . . , G4 are connected to a surrounding circuit elements by a bonding wire etc., and the drain terminal electrode D is also connected to a surrounding circuit elements chip by a bonding wire etc.
As mentioned above, since a plurality of fingers of the gate electrode 24, the source electrode 20, and the drain electrode 22 are placed on one continuous active area in the conventional semiconductor device, it is difficult to distribute heat sources generated in the active areas AA. The operational performance of a power amplification element with high exothermic density, such as GaN based FETs, was deteriorated in particular remarkably.
For example, it is possible by extending electrode spacing between the source electrode 20 and the gate electrode 24, between the drain electrode 22 and the gate electrode 24, etc. to distribute the heat source generated in the active area AA to some extent. However, the effect becomes small by a reciprocal of a distance of the electrode spacing.
That is, in order to set up the same current capacity by using a configuration which extends the electrode spacing, since finger length becomes long, parasitic capacitance increases. Moreover, since finger length of a gate becomes long at about 2 times by using a configuration which extends the electrode spacing, a conductor loss of the gate electrode finger itself becomes large. Moreover, since finger of the gate electrode 24 and the drain electrode 22 becomes long at about 2 times by using the configuration which extends the electrode spacing, a conductor loss of gate electrode finger and the drain electrode finger itself becomes large.                Patent Document 1:        
Japanese Patent Application Laying-Open Publication No. H02-288409                Patent Document 2:        
Japanese Patent Application Laying-Open Publication No. 2001-28425                Patent Document 3:        
Japanese Patent Application Laying-Open Publication No. S57-160148                Patent Document 4:        
Japanese Patent Application Laying-Open Publication No. H08-213409                Patent Document 5:        
U.S. Pat. No. 7,135,747